1. Field of the Invention
The invention of the present application relates to a method of forming a pattern on manufacturing a semiconductor device.
2. Description of the Related Art
For a miniaturization of a semiconductor device, technology of forming fine pattern has to be developed. Presently, a resist patterned by lithography is generally used as masking layer in etching for forming a pattern. Thus, minuteness of a pattern will be limited by resolution limit of lithography so long as one uses lithography as it is presently used.
Some related art (e.g., Japanese Patent Laid-Open Publication No. 364021/1992) discloses an example of forming a pattern having a narrower interval than the resolution limit of lithography, wherein the opening of the resist patterned up to the resolution limit of lithography is narrowed by softening and deforming (by heating) and etching is effected using as mask this deformed resist.
In this related art, however, while the width of the opening can be narrowed, the width of a covering portion on the resist is increased so that the width of remaining portions after etching becomes increased. For this reason, the pitch of line-and-space pattern remained unchanged, i.e., as a whole, no formation of pattern with higher resolution than the resolution limit of lithography was achieved.